1. Field of the Invention
The present invention generally relates to a memory device using a multiple layer nano tube cell, and more specifically, to a technology of effectively arranging a cross point cell array comprising a capacitor and a PNPN nano tube switch which does not require a gate control signal, thereby reducing whole memory size.
2. Description of the Prior Art
Generally, a Dynamic Random Access Memory (hereinafter, referred to as ‘DRAM’) comprises a transistor for performing a switching operation depending on a state of a word line to connect a capacitor to a bit line, and the capacitor connected between a plate line and one terminal of the transistor.
Here, a switching device of a conventional DRAM cell is a NMOS transistor whose switching operation is controlled by a gate control signal. However, when a cell array is embodied by using the NMOS transistor as a switching device, the whole chip size is increased.
Meanwhile, a refresh characteristic of the DRAM cell is determined by the leakage current characteristic of the NMOS transistor. When the channel length of the NMOS transistor is decreased to a nanometer (1/1 billion) scale, short channel leakage current increases more by the current characteristic of a sub threshold voltage (Sub Vt) of the NMOS transistor. As a result, it is difficult to satisfy the refresh characteristic of the DRAM cell. Also, junction leakage current is generated in a storage node terminal which occupies a relatively large area in the DRAM cell.
Therefore, it is necessary to embody a cross point cell using a capacitor and a PNPN nano tube switch which does not require an additional gate control signal, and to reduce the whole chip size by effectively positioning the cross point cell and a circuit device region for controlling the same.